This invention relates to a semiconductor device, and particularly to semiconductor device a having a so-called `pad`.
Along with a rapid expansion of the portable information terminal market in recent years, the realization of high integration, high speed and low power consumption of VLSI circuits has been progressing markedly. This can be said to be a result of much research relating to performance improvements based on increases in the speed and miniaturization of individual devices constituting VLSI circuits.
A pad of the related art will now be described with reference to the schematic sectional construction view of FIG. 1.
As shown in FIG. 1, for example an N-type epitaxial layer (112) is formed on a P-type substrate 111, and a P-type isolating diffusion layer 113 and a device separation oxide film 114 formed by LOCOS (Local Oxidation of Silicon) are formed on this N-type epitaxial layer (112). Also, a so-called field oxide film 115 is formed on the device separation oxide film 114. A pad 116 of a three-layer aluminum structure is formed on the field oxide film 115.
However, particularly in the realization of high speed, there have been cases where even if the speed of the internals of an IC is increased it is not possible to improve the operating speed of the IC itself because its signal processing speed is attenuated by substrate capacitance parasitically connected to the wire bonding regions, or pads, of the IC.
In the operation of an ordinary IC comprising a semiconductor device having the pad structure described above in reference to the related art, power is supplied to the device through a wire bonded to the surface of a conducting layer constituting the uppermost layer of the pad, and the P-type substrate is grounded at all times. Consequently, the conducting layers making up the three-layer aluminum structure pad become an upper electrode, the P-type substrate and the P-type isolating diffusion layer act as a lower electrode, and the field oxide film and the device separation oxide film act as an oxide film capacitance. As a result, because this amounts to a capacitance being connected in series between the pad and the P-type substrate, improvement of the operating speed of the IC has been hindered.
This parasitically connected oxide film capacitance decreases with reductions in pad surface area accompanying increased integration of VLSI circuits but increases with reductions in the thickness of the field oxide film accompanying voltage reductions and greater miniaturization.
Thus, in the related art structure, there has been a limit to reduction of the parasitic capacitance connected to the pad, and improving IC operating speeds along with increases in device speeds has been problematic.